Breadboard Bits - Osiris

An assortment of prototypes of Osiris parts. Clockwise from top left: testing power supply, breadboarded CPU and RTC, system bus/backplane, partial ICE board.
I decided that it was about time for me to start making a homebrew computer of my own. I started designing and specifying, and dug out whatever parts I had on hand. The result is the Osiris, which is still an active work in progress. As such, this page will be updated as work continues.

The basic architecture is based around a Z80 CPU running at 4MHz, a memory management unit (MMU), and a DRAM interface. The DRAM interface drives 8MB of 30-pin SIMM's (a bank of two slots). The initialization code and operating system is stored in a 29F040 flash RAM.

Programming of the system is accomplished by use of an In-Circuit Emulator (ICE), which allows an external computer to take control of the CPU bus. This allows not only flash programming, but full control of on-board peripherals, to assist in development of the critical peripheral set.

It's worth noting that I have started mounting my stand-alone boards, on standoffs, to an acrylic baseplate, with rubber feet on the bottom. It keeps things away from the solder-side, and looks nice besides.

In-Circuit Emulator

The ICE board after a lot more work. At this point, the display section is completely functional and the PC-facing interface is partially complete. The empty sockets are for control electronics and buffering.
The ICE board is a relatively simple design.

The connector on the bottom of the board connects to a parallel port of a PC. The top connector runs to the Osiris system itself, and contains most of the signals of the Z80 bus.

The top half is composed of an oscillator, a set of column driver transistors, a quadrature clock generator, and a large 8-bit 4-input MUX. A pair of 4-digit seven segment LED displays track the data on the external bus. The row driving is accomplished with a pair of 74LS48's with current buffering through a pair of 74LS641's. The 641's have beefy output drivers that can handle directly driving (or, in this case, shunting) the LED displays.

The bottom half is essentially a 32-bit shift register with a set of buffers to drive the CPU bus. Thanks to a particularly large surplus order, I have more 74LS374's and 74LS245's than I know what to do with, and I made liberal use of that fact on this board.

The architecture is heavily inspired by jTag boundary scan, and while not quite as flexible, does allow me to do a considerable amount of testing. In fact, it is flexible enough to emulate all the I/O of the Z80 chip, with the notable exception of the DRAM refresh signals, which are time critical.

The ICE board again. This time, the main shift register is complete, the control signals have been added, and the output buffers are half complete.
Between the top and bottom halves is the output buffer. This actually controls the output lines of the top connector, when engaged by the controlling computer. The Osiris CPU mediates the bus access even for the ICE board. The system asserts the Z80 BUSRQ line and waits for the BUSACK before engaging the output buffers.

The buffer is composed of 3 8-bit output-only buffers, and a bidirectional buffer. The first two control the address bus, the third drives the control signals, and the bidirectional buffer drives the IO bus.

All the usual frills are provided, including a lamp test button just under the LED decoding hardware.